FIG. 1 shows a memory cell in a known conventional MOS static random access memory, hereinafter called RAM, and in which resistors serve as a load. A static RAM is comprised of a plurality of such memory cells. In FIG. 1, reference numerals 1 to 4 denote n-channel MOS transistors, hereinafter referred to as MOST's, wherein 1 and 2 denote transfer MOST's, and 3 and 4 denote drive MOST's. Reference numerals 5 and 6 denote data lines, 7 denotes a word line, 8 and 9 denote load resistors, and data stored in the data storage nodes 12, 13 are retained by supplying an electric current from a power line 10 (potential V.sub.CC). Reference numeral 11 denotes a ground line (potential V.sub.SS). The load resistors 8, 9 are obtained by forming a polycrystalline silicon layer that is formed through the process of forming the gates of MOST's 1 to 4, or by forming a laminated polycrystalline silicon layer that is formed through a process different from the process of forming the gates, and by leaving a portion of the polycrystalline silicon layer as an intrinsic semiconductor or as a low doped region. The data is written onto the memory cell or is read out therefrom through data lines 5, 6 by raising the potential of the word line 7 from a low level to a high level.